Multicore Systems On-Chip: Practical Software/Hardware Design

Description: Please refer to the section BELOW (and NOT ABOVE) this line for the product details - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Title:Multicore Systems On-Chip: Practical Software/Hardware DesignISBN13:9789491216916ISBN10:9491216910Author:Ben Abdallah, Abderazek (Author)Description:System On Chips Designs Have Evolved From Fairly Simple Unicore, Single Memory Designs To Complex Heterogeneous Multicore Soc Architectures Consisting Of A Large Number Of Ip Blocks On The Same Silicon To Meet High Computational Demands Posed By Latest Consumer Electronic Devices, Most Current Systems Are Based On Such Paradigm, Which Represents A Real Revolution In Many Aspects In Computing The Attraction Of Multicore Processing For Power Reduction Is Compelling By Splitting A Set Of Tasks Among Multiple Processor Cores, The Operating Frequency Necessary For Each Core Can Be Reduced, Allowing To Reduce The Voltage On Each Core Because Dynamic Power Is Proportional To The Frequency And To The Square Of The Voltage, We Get A Big Gain, Even Though We May Have More Cores Running As More And More Cores Are Integrated Into These Designs To Share The Ever Increasing Processing Load, The Main Challenges Lie In Efficient Memory Hierarchy, Scalable System Interconnect, New Programming Paradigms, And Efficient Integration Methodology For Connecting Such Heterogeneous Cores Into A Single System Capable Of Leveraging Their Individual Flexibility Current Design Methods Tend Toward Mixed Hwsw Co-Designs Targeting Multicore Systems On-Chip For Specific Applications To Decide On The Lowest Cost Mix Of Cores, Designers Must Iteratively Map The Device's Functionality To A Particular Hwsw Partition And Target Architectures In Addition, To Connect The Heterogeneous Cores, The Architecture Requires High Performance Complex Communication Architectures And Efficient Communication Protocols, Such As Hierarchical Bus, Point-To-Point Connection, Or Network-On-Chip Software Development Also Becomes Far More Complex Due To The Difficulties In Breaking A Single Processing Task Into Multiple Parts That Can Be Processed Separately And Then Reassembled Later This Reflects The Fact That Certain Processor Jobs Cannot Be Easily Parallelized To Run Concurrently On Multiple Processing Cores And That Load Balancing Between Processing Cores - Especially Heterogeneous Cores - Is Very Difficult Binding:Hardcover, HardcoverPublisher:SPRINGER NATUREPublication Date:2013-08-05Weight:1.2 lbsDimensions:0.9'' H x 9.2'' L x 6.3'' WNumber of Pages:273Language:English

Price: 59.58 USD

Location: USA

End Time: 2024-08-19T13:43:48.000Z

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